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HI3050
August 1997
Triple 10-Bit, 50 MSPS, High Speed, 3-Channel D/A Converter
Description
The HI3050 is a triple, 10-bit D/A converter, fabricated in a silicon gate CMOS process, ideally suited for RGB video applications. The converter incorporates three 10-bit input data registers with a common blanking capability, forcing all outputs to 0mA. The HI3050 features low glitch, high impedance current outputs and single 5V supply operation. Low current inputs accept standard TTL/CMOS levels. The architecture is a current cell arrangement providing low differential and integral linearity errors. The HI3050 requires a 2V external reference and a set resistor to control the output current. The HI3050 also features a chip enable/disable pin for reducing power consumption (<5mW) when the part is not in use. The HI3050 can generate RS-343A and RS-170 compatible video signals into doubly terminated and singly terminated 75 loads.
Features
* Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . Triple 10-Bit * Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . . . 50MHz * 3-Channel, RGB, I/O * RS-343A/RS-170 Compatible Outputs * Low Power Consumption (Typ) . . . . . . . . . . . . .500mW * Differential Linearity Error . . . . . . . . . . . . . . . 0.5 LSB * Low Glitch Energy * CMOS Compatible Inputs * Direct Replacement for Sony CXD2308
Applications
* NTSC, PAL, SECAM Displays * High Definition Television (HDTV) * Presentation and Broadcast Video * Image Processing * Graphics Displays
Ordering Information
PART NUMBER HI3050JCQ TEMP. RANGE (oC) -20 to 75 PACKAGE 64 Ld MQFP PKG. NO. Q64.14x20-S
Pinout
HI3050 (MQFP) TOP VIEW
DVDD AVDD AVDD BOUT BOUT AVDD AVDD GOUT GOUT AVDD AVDD ROUT ROUT R0 (LSB) R1 R2 R3 R4 R5 R6 R7 R8 R9 (MSB) G0 (LSB) G1 G2 G3 G4 G5 G6 G7 G8 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 50 2 49 3 48 4 47 5 46 6 45 7 44 8 43 9 42 10 41 11 40 12 39 13 38 14 37 15 36 16 35 17 18 34 19 33 20 21 22 23 24 25 26 27 28 29 30 31 32 G9 (MSB) B0 (LSB) B1 B2 B3 B4 B5 B6 B7 B8 B9 (MSB) BLANK CE
AGND COMP B VREF OUT B COMP G VREF OUT G COMP R VREF OUT R VREFB VREFG VREFR FS ADJUST B FS ADJUST G FS ADJUST R AGND VBIAS DGND BCLK GCLK RCLK
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
3936.2
10-1
HI3050 Functional Block Diagram
64 R0 (LSB) R1 R2 R3 R4 R5 R6 R7 R8 R9 G0 (LSB) G1 G2 G3 G4 G5 G6 G7 G8 G9 B0 (LSB) B1 B2 B3 B4 B5 B6 B7 B8 B9 1 2 3 4 5 LATCHES 6 7 8 9 10 11 12 13 14 15 LATCHES 16 17 18 19 20 21 22 23 24 25 LATCHES 26 27 28 29 30 DECODER CURRENT CELLS (FOR FULL SCALE) BIAS VOLTAGE GENERATOR CLOCK GENERATOR + 49 44 41 VREF OUT B VREFB FS ADJUST B DECODER 35 BCLK 6 MSBs CURRENT CELLS DECODER CURRENT CELLS (FOR FULL SCALE) 4 LSBs CURRENT CELLS CLOCK GENERATOR + 47 43 40 54 55 50 60 61 VREF OUT G VREFG FS ADJUST G AVDD AVDD COMP B BOUT BOUT DECODER 34 GCLK 6 MSBs CURRENT CELLS DECODER CURRENT CELLS (FOR FULL SCALE) 4 LSBs CURRENT CELLS CLOCK GENERATOR + 45 42 39 58 59 48 56 57 VREF OUT R VREFR FS ADJUST R AVDD AVDD COMP G GOUT GOUT DECODER 33 RCLK 6 MSBs CURRENT CELLS 62 4 LSBs CURRENT CELLS 63 46 52 53 DVDD AVDD AVDD COMP R ROUT ROUT
37 38 51 36
VBIAS AGND AGND DGND
BLANK CE
31 32
10-2
HI3050 Pin Descriptions and Equivalent Circuits
PIN NO. 1 - 10 11 - 20 21 - 30 SYMBOL R0 - R9 G0 - G9 B0 - B9
1 TO 30
EQUIVALENT CIRCUIT
DVDD
DESCRIPTION Digital Inputs.
DGND
31
BLANK
DVDD
Output Blanking Input. High: Outputs Set to 0mA. Low: Normal Output Operation.
31
DGND
37
VBIAS
DVDD
DVDD
Internal Bias Decoupling. Connect a 0.1F decoupling capacitor to DGND.
37
+
-
DGND
33 34 35
RCLK GCLK
33
DVDD
Clock Inputs. All input pins are TTL/CMOS compatible.
BCLK
34 35 DGND
36 38, 51 32
DGND AGND CE
DVDD
Digital Ground. Analog Ground. Chip Enable pin. High: Part Disabled Low: Part Enabled
32
DGND
54, 55, 58, 59, 62, 63
AVDD
Analog Power Supply.
10-3
HI3050 Pin Descriptions and Equivalent Circuits
PIN NO. 45 47 49 46 48 50 39 40 41 42 43 44 SYMBOL VREF OUT R VREF OUT G
45
(Continued) DESCRIPTION Reference Output. Typically connected to the Reference Decoupling inputs (COMP R, COMP G, COMP B). See Figures 11 and 12 for various configurations. Reference Decoupling. Connect a decoupling capacitor (0.1F) to reduce noise on reference to AVDD .
EQUIVALENT CIRCUIT
AVDD
VREF OUT B COMP R COMP G COMP B FS ADJUST R
47 49 AGND AVDD
46
FS ADJUST G FS ADJUST B VREFR VREFG VREFB
48 50 AGND AVDD
Full Scale Adjust. Typically connect a 1.2k resistor, RSET , to AGND. RSET is used to determine full scale output current. Voltage Reference Input. Typically set to 2V and determines full scale output current.
39 40 41 AGND AVDD +
V REF I OUT ( Full Scale ) = -------------- x 16 R SET
-
42 43 44 AGND
52 56 60 53 57 61
ROUT GOUT BOUT ROUT GOUT BOUT
AGND AVDD 52 56 60 AVDD
Current Outputs.
Inverted Current Outputs.
53 57 61 AGND
64
DVDD
Digital Power Supply.
10-4
HI3050
Absolute Maximum Ratings
TA = 25oC
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (MQFP - Lead Tips Only) Clock Pulse Width (tPW1 , tPW0) . . . . . . . . . . . . . . . . . . . .10ns (Min) Temperature Range (TOPR) . . . . . . . . . . . . . . . . . . . .-20oC to 75oC
Digital Supply Voltage, DVDD to DGND . . . . . . . . . . . . . . . . . . . +7V Analog Supply Voltage, AVDD to AGND . . . . . . . . . . . . . . . . . . . +7V Digital Input Voltages . . . . . . . . . . . . . . . . . . . . . . . . DVDD to DGND Analog Output Current (IOUT) . . . . . . . . . . . . . . . . . . . . . . . . . 30mA
Operating Conditions
Supply Voltage, AVDD , AVSS . . . . . . . . . . . . . . . . . . .4.75V to 5.25V DVDD , DVSS . . . . . . . . . . . . . . . . . . .4.75V to 5.25V
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER SYSTEM PERFORMANCE Resolution Maximum Conversion Speed Integral Linearity Error, INL Differential Linearity Error, DNL Output Offset Voltage, VOS
AVDD = +5V, DVDD = +5V, fCLK = 50MHz, RL = 75, VREF = 2V, RSET = 1.2k, TA = 25oC TEST CONDITIONS MIN TYP MAX UNITS
50 "Best Fit" Straight Line -2.0 -0.5 (Note 2) 0 1.8 -
10 1.5 27 1.9 2.5
2.0 0.5 1 3 30 2.0 -
Bits MSPS LSB LSB mV % mA V V
Output Full Scale Ratio Error, FSRE Full Scale Output Current, IFS Full Scale Output Voltage, VFS Output Voltage Compliance Range DYNAMIC CHARACTERISTICS Glitch Energy, GE Settling Time Crosstalk DIGITAL INPUTS Input Logic High Voltage, VIH Input Logic Low Voltage, VIL Input Logic Current, IIH Input Logic Current, IIL Digital Input Capacitance, CIN TIMING CHARACTERISTICS Data Setup Time, tSU Data Hold Time, tHLD Propagation Delay Time, tPD Clock Pulse Width, tPW1, tPW0 POWER SUPPLY CHARACTERISITICS Total Supply Current, AIDD + DIDD Analog Supply Current, AIDD Digital Supply Current, DIDD Power Dissipation NOTE: 2. Configured for Common Reference.
IOUT = 13.5mA 10MHz Output Sine Wave -
50 40 50
-
pV/s ns dB
2.0 -5 -
10
0.8 5 -
V V A A pF
See Figure 1 See Figure 1 See Figure 1 See Figure 1
10
5 1 10 -
7 3 -
ns ns ns ns
-
100 92 8 500
110 550
mA mA mA mW
Full Scale Voltage of Channel F SRE = ----------------------------------------------------------------------------------------------------------------- - 1 x 100% Average Full Scale Voltage of All Channels
10-5
HI3050 Timing Diagram
tPW1 tPW0
CLK
50%
tSU tHLD R9-R0 G9-G0 B9-B0
tSU tHLD
tSU tHLD
tPD ROUT GOUT BOUT
100%
50%
0% tPD tPD
FIGURE 1. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM
Typical Performance Curves
80 110 70 SUPPLY CURRENT (mA)
CROSSTALK (dB)
60
50 VDD = 5.0V, TA = 25oC 40 100K 1M OUTPUT FREQUENCY (Hz) 10M
VDD = 5.0V, fCLK = 50MHz VREF = 2.0V 100
-20
0
25
50
75
AMBIENT TEMPERATURE (oC)
FIGURE 2. CROSSTALK vs OUTPUT FREQUENCY
FIGURE 3. SUPPLY CURRENT vs AMBIENT TEMPERATURE
70
1.9 FULL-SCALE VOLTAGE (V)
65 60 SFDR (dB) VDD = 5.0V, VREF = 2.0V 55 50 45 40 35 30 0.1
1.8
-20
0
25
50
70
1.0 OUTPUT FREQUENCY (MHz)
10.0
AMBIENT TEMPERATURE (oC)
FIGURE 4. FULL SCALE VOLTAGE vs AMBIENT TEMPERATURE
FIGURE 5. SFDR vs OUTPUT FREQUENCY
10-6
HI3050
DAC INPUT/OUTPUT CODE TABLE (NOTE 1) INPUT CODE MSB D9 1 D8 1 D7 1 D6 1 D5 1 * * * 1 0 0 0 0 * * * 0 NOTE: 1. VREF = 2.0V, RSET = 1.2K, RLOAD = 75. 0 0 0 0 0 0 0 0 0 0V 0 0 0 0 0 1.0V D4 1 D3 1 D2 1 D1 1 LSB D0 1 OUTPUT VOLTAGE 2.0V
Detailed Description
The HI3050 contains three matched, individual, 10 bit current output digital-to-analog converters. The DACs can convert at 50MHz and run on +5V for both the analog and digital supplies. The architecture is a current cell arrangement. 10-bit linearity is obtained without laser trimming due to an internal calibration. Digital Inputs The digital inputs to the HI3050 have TTL level thresholds. Due to the low input currents CMOS logic can be used as well. The digital inputs are latched on the rising edge of the clock. To reduce switching noise from the digital data inputs, a series termination resistor is the best solution. Using a 50 to 130 resistor in series with the data lines, the edge rates are slowed. Slower edge rates reduce the amount of overshoot and undershoot that directly couples through the lead frame of the device. TTL drivers such as the 74ALS or 74F series or CMOS logic series drivers, ACT, AC, or FCT, are excellent for driving the TTL/CMOS inputs of the converter. Clocks and Termination The HI3050 clock rate can run to 50MHz, therefore, to minimize reflections and clock noise into the part, proper termination should be considered. In PCB layout clock traces should be kept short and have a minimum of loads. To guarantee consistent results from board to board controlled impedance traces should be used with a characteristic line impedance. To terminate the clock line, a shunt terminator to an AC ground is the most effective type at a 50MHz clock rate. Shunt termination is best used at the receiving end of the transmission line or as close to the HI3050 CLK pin as possible.
HI3050 DAC CLK RT = 50
Rise and fall times and propagation delay of the line will be affected by the Shunt Terminator. The terminator can be connected to DGND. Power Supplies To reduce power supply noise, separate analog and digital power supplies should be used with 0.1F and 0.01F ceramic capacitors placed as close to the body of the HI3050 as possible on the analog (AVDD) and digital (DVDD) supplies. The analog and digital ground returns should be connected together at the device to ensure proper operation on power up. Reference The HI3050 DACs have their own references and can be set individually, see Figure 13. The three references can also share a common reference voltage, see Figure 12. A shared reference gives DAC to DAC matching of 1.5%, typically. The HI3050 requires an external reference voltage to set the full scale output current. The external reference voltage is connected to the VREF inputs (VREFR , VREFG , and VREFB). The Full Scale Adjust input (FS ADJUST R, FS ADJUST G, FS ADJUST B) should be connected to AGND through a 1.2k resistor, RSET . The reference outputs (VREF OUT R, VREF OUT G, VREF OUT B) should be connected to the decoupling input (COMP R, COMP G, COMP B) and decoupled to AVDD with a 0.1F capacitor. This improves settling time by decoupling switching noise from the reference output of the HI3050. The full scale output current is controlled by the voltage reference pin and the set resistor (RSET). The ratio is:
IOUT (Full Scale) = (VREF/RSET) x 16, IOUT is in mA (EQ.1)
Blanking Input
ZO = 50
The BLANK input, when pulled high, will force the outputs of all three DACs to 0mA. Chip Enable The chip enable input, CE, will shut down the HI3050 causing the outputs to go to 0mA. The analog and digital supply current will decrease to less than 1mA, reducing power for low power applications.
FIGURE 6. AC TERMINATION OF THE HI3050 CLOCK LINE
10-7
HI3050
Outputs The HI3050 DAC outputs are complementary current outputs. Current is steered to either IOUT or IOUT in proportion to the digital input code. The current output can be converted to a voltage by using a resistor load or I/V converting op amp. If only one output of a converter is being used, the unused output can be connected to ground or to a load equal to the used output. The output voltage when using a resistor load is:
VOUT = IOUT x ROUT (EQ. 2)
to change before another. To minimize this, the Intersil HI3050 employs an internal register, just prior to the current sources, that is updated on the clock edge. In measuring the output glitch of the HI3050, the output is terminated into a 75 load. The glitch is measured at the major carries throughout the DACs output range.
HI3050 IOUT 75
50MHz LOW PASS FILTER
SCOPE
The compliance range of the outputs is from 0V to +2.5V. To convert the output current of the D/A converter to a voltage a load resistor followed by a buffer amplifier can be used as shown in Figure 5. The DAC needs a 75 termination resistor on the IOUT pin to ensure proper settling.
HI3050 DAC IOUT 75 1/3 HA5013 + 75
50
FIGURE 8. GLITCH TEST CIRCUIT
-
75
The glitch energy is calculated by measuring the area under the voltage-time curve. Figure 9 shows the area considered as glitch when changing the DAC output. Units are typically specified in picoVolt/seconds (pV/s).
V
HEIGHT (H)
FIGURE 7. HIGH SPEED CURRENT TO VOLTAGE CONVERSION
Glitch The output glitch of the HI3050 is measured by summing the area under the switching transients after an update of the DAC. Glitch is caused by the time skew between bits of the incoming digital data. Typically the switching time of digital inputs are asymmetrical meaning that the turn off time is faster than the turn on time (TTL designs). Unequal delay paths through the device can also cause one current source
WIDTH (W) GLITCH AREA = 1/2 (H X W) T (ps)
FIGURE 9. GLITCH ENERGY
Test Circuits
R0 - R9 1 - 10 G0 - G9 11 - 20 B0 - B9 21 - 30 31 BLK B0 60 0.1F 32 CE B0 61 37 VB DGND 33 RCLK CLK 50MHz SQUARE WAVE 34 GCLK 35 BCLK 46, 48, 50 45, 47, 49 42 - 44 39 - 41 1.2k AVDD 0.1 F 2V 75 AGND AGND R0 52 R0 53 AGND G0 56 G0 57 75 OSCILLOSCOPE 75
10-BIT COUNTER WITH LATCH
FIGURE 10. MAXIMUM CONVERSION SPEED TEST CIRCUIT
10-8
HI3050 Test Circuits
(Continued)
10-BIT COUNTER WITH LATCH
R0 - R9 1 - 10 G0 - G9 11 - 20 B0 - B9 21 - 30 31 BLK
R0 52 R0 53
75 AGND
G0 56 G0 57 B0 60 75 AGND AVDD 46, 48, 50 0.1 F 2V 75 AGND
OSCILLOSCOPE
DELAY CONTROLLER
0.1F
32 CE B0 61 37 VB
DGND 33 RCLK CLK 50MHz SQUARE WAVE DELAY CONTROLLER 34 GCLK 35 BCLK
45, 47, 49 42 - 44 39 - 41
1.2k
FIGURE 11. SETUP HOLD TIME AND GLITCH ENERGY TEST CIRCUIT
ALL "1" DIGITAL WAVEFORM GENERATOR
R0 - R9 1 - 10 G0 - G9 11 - 20 B0 - B9 21 - 30 31 BLK
R0 52 R0 53
75 AGND
G0 56 G0 57 B0 60 75 AGND AVDD 46, 48, 50 0.1 F 2V 75 AGND
OSCILLOSCOPE
0.1F
32 CE B0 61 37 VB
DGND 33 RCLK CLK 50MHz SQUARE WAVE 34 GCLK 35 BCLK
45, 47, 49 42 - 44 39 - 41
1.2k
FIGURE 12. CROSSTALK TEST CIRCUIT
10-9
HI3050 Applications Circuits
1k 0.1 F 1.2k NC ROUT 75 GOUT 75 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 52 32 53 31 54 30 55 29 56 28 57 27 58 26 59 25 60 24 61 23 62 22 63 21 64 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 NC NC NC CLOCK INPUT
0.1F
BOUT 75
B CHANNEL INPUT
AVDD AGND
DVDD DGND
R CHANNEL INPUT
G CHANNEL INPUT
FIGURE 13. COMMON VOLTAGE REFERENCE
1k
1k
1k
0.1 0.1F F
0.1 1.2k 1.2k 1.2k F
0.1 F
CLOCK INPUT
ROUT 75 GOUT 75 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 52 32 53 31 54 30 55 29 56 28 57 27 58 26 59 25 60 24 61 23 62 22 63 21 64 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
BOUT 75
B CHANNEL INPUT
AVDD AGND
DVDD DGND
R CHANNEL INPUT
G CHANNEL INPUT
FIGURE 14. INDEPENDENT REFERENCES
10-10
HI3050 Definition of Specifications
Integral Linearity Error, INL, is the measure of the worst case point that deviates from a best fit straight line of data values along the transfer curve. Differential Linearity Error, DNL, is the measure of the step size output deviation from code to code. Ideally the step size should be 1 LSB. A DNL specification of 1 LSB or less guarantees monotonicity. Crosstalk, is the undesirable signal coupling from one channel to another. Feedthrough, is the measure of the undesirable switching noise coupled to the output. Output Voltage Full Scale Settling Time, is the time required from the 50% point on the clock input for a full scale step to settle within an 1/2 LSB error band. Output Voltage Small Scale Settling Time, is the time required from the 50% point on the clock input for a 100mV step to settle within an 1/2 LSB error band. This is used by applications reconstructing highly correlated signals such as sine waves with more than 5 points per cycle. Glitch Energy, GE, is the switching transient appearing on the output during a code transition. It is measured as the area under the curve and expressed as a Volt-Time specification. Differential Gain, DG, is the peak difference in chrominance amplitude (in percent) at two different DC levels. Differential Phase, DP, is the peak difference in chrominance phase (in degrees) at two different DC levels. Signal to Noise Ratio, SNR, is the ratio of a fundamental to the noise floor of the analog output. The first 5 harmonics are ignored, and an output filter of 1/2 the clock frequency is used to eliminate alias products. Total Harmonic Distortion, THD, is the ratio of the DAC output fundamental to the RMS sum of the harmonics. The first 5 harmonics are included, and an output filter of 1/2 the clock frequency is used to eliminate alias products. Spurious Free Dynamic Range, SFDR, is the amplitude difference from a fundamental to the largest harmonically or non-harmonically related spur. A sine wave is loaded into the D/A and the output filtered at 1/2 the clock frequency to eliminate noise from clocking alias terms. Intermodulation Distortion, IMD, is the measure of the sum and difference products produced when a two tone input is driven into the D/A. The distortion products created will arise at sum and difference frequencies of the two tones. IMD is:
20 Log (RMS of Sum and Difference Distortion Products) IMD = -----------------------------------------------------------------------------------------------------------------------------------------------------( RMS Amplitude of the Fundamental )
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
10-11

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